The present invention relates to a switch matrix among tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data which are structured according to SDH protocol, said switch matrix comprising a set of parallel branches, with each branch comprising at least a first space stage able to select and pack from the input data flow a subset of data to be exchanged, a second time stage able to store the data subset to be exchanged and comprising a random access memory device, associated with a write memory and a read memory, said write memory and read memory being driven by a microprocessor and a master counter. Hereafter, the term xe2x80x9ctelecommunication networksxe2x80x9d will mean synchronous signal carrying networks, specifically according to SDH (Synchronous Digital Hierarchy) standard.
Telecommunication networks are equipped with elements located in the switching stations, called xe2x80x9cswitch matrixesxe2x80x9d, which can carry out connections between communication circuits, the so-called xe2x80x98tributariesxe2x80x99, with the aim of putting users in communication. Switch matrixes operate according to users"" requests or under direct control of the network manager, establishing the so-called semi-permanent connections.
As known, SDH frames, e.g. frames STM-1 generally consist of a subframe set called Virtual Containers, which in turn consist of lower order Virtual Containers according to a hierarchic structure. Therefore, an SDH frame will appear like a subframe time sequence and a switch matrix fulfills its function of connection maker by reassigning the location of Virtual Containers within the SDH frame.
The most common manner for obtaining a switch matrix consists in employing a random access memory element, i.e. a RAM memory, equipped with two access ports or gates, i.e. at least a write port and a read port. RAM memories are known, for instance, having 16 write ports and 8 read ports. Such a RAM memory is able to exchange all Virtual Containers contained in the input frames and generate 8 output frames. Moreover, it is a strictly nonblocking structure, i.e. always able to establish connections without altering other connections already established. On the other hand, a RAM memory requires that during write operations a proper counter will sequentially supply the addresses where to write input data in the memory element. A read control memory containing read addresses, i.e. the data read order is also needed to rearrange output frames to obtain desired connections.
However, even if the use of a RAM memory according to the above mode is advantageous for its simple implementation, considerable drawbacks exist since RAM memories of the type described above are not conventional memories, i.e. they need a design strictly associated with the type of switch matrix to be obtained.
The use of a switch matrix of a so-called xe2x80x9cknock-out switchxe2x80x9d type is known. This is a multistage connection type, where the main modular element consists of a space-time-space matrix. The xe2x80x9cknock-out switchxe2x80x9d allows for employing a memory so sized as to store the data exclusively related to reassignment.
The purpose of the first space stage is to adapt the input data flow to obtain a sequential filling of a elastic memory, which represents the subsequent time stage.
The second stage, i.e. the so-called subsequent time stage, operates the exchange of the time position of the tributaries which have been sequentially randomly introduced in the output frame. It consists of a sequential write/programmable read-memory.
The third stage, if required, detects the data to be routed to several outputs when the second stage has an output capacity greater than a frame.
FIG. 1 shows a block diagram of a xe2x80x9cknock-out switchxe2x80x9d KS according to the known state of the art.
As it can be noted an input data flow DIN containing an integer number N of frames ST is available. Each frame ST is divided internally in time units TS, identifying the various bytes to be switched. In the following description the number N will be equal to 8, unless otherwise indicated. Input data flow DIN is sent to a number m of branches BR1...BRm in parallel. The same structure is duplicated on each of said branches BR1...BPm, said structure comprising a concentrator rotator block CR controlled by a write control memory WCM through a write sequence WW. Said write sequence WW contains information where active bytes are located, i.e. the pertaining bytes DSC for the exchange. A buffer BUF, namely a temporary transit memory is provided downstream the concentrator rotator block CR. Then a memory DTRAM driven by a read control memory RCM will follow through a read word RR, which contains the addresses to be read in the memory DTRAM. Said memory DTRAM which is an elastic multiport RAM memory is provided with a plurality of outputs OUT. Said outputs OUT are N/m for each memory DTRAM, so that the memory DTRAM1 will have OUT0 to OUTN/mxe2x88x921 outputs and memory DTRAMm OUTN(mxe2x88x921)/m to OUTNxe2x88x921 outputs. Thus, in the knock-out switch KS what represented a single memory matrix is divided in m branches BR1...BRm. Each of said branches BR1...BRm only elaborates sets of time units or subframes ST relating to a group of N/m outputs OUT. This will obviously allow the use of smaller memories DTRAM as a function of the number m of branches BR1...BRm being chosen.
The concentrator rotator block CR is substantially a combinatorial network with N inputs and outputs. The concentrator rotator block CR has to select the bytes DSC relating to its branch BR in the data flow DIN, place them in adjacent positions and then rotate the thus obtained set of bytes to completely fill the memory DTRAM. FIG. 2 shows operation of a concentrator rotator block CR with N=5, in six subsequent time units TS. Pertaining bytes DSC spread at the input of the concentrator rotator block CR are concentrated and properly placed inside the memory DTRAM through a circular shift operation, i.e. a rotation. Naturally, during these operations the concentrator rotator block CR is driven by the write sequence WW.
The subsequent buffer BUF is required should the memory DTRAM only allow to write words of a predetermined length. Since the number of output bytes from the concentrator rotator block CR is variable in time, the bytes are temporary stored in the buffer BUF till a full word is formed. As soon as this happens, the word obtained is transferred to the memory DTRAM.
The concentrator rotator block CR is driven by the write control memory WCM, which is a memory whose depth is equal to the number of time units TS forming the frame ST and a word length equal to the one of the write sequence WW of N bits. Being said j and k generally two integer indexes, the j-th bit of the k-th write sequence WW in the write control memory WCM is set at 1 if the byte in the k-th time unit TS of the j-th input frame ST has to be saved in the memory DTRAM belonging to the same branch of the write control memory WCM under consideration.
When the memory DTRAM is completely filled, it is read with random access, according to the contents of the read control memory RCM.
Also the xe2x80x9cknock-out switchxe2x80x9d has some drawbacks, even if it allows subdivision of the memory in a plurality of smaller memories.
When using a RAM standard memory, each byte corresponding to a Virtual Container is always stored in the same memory location. This does not occur for the knock-out switch, due to concentration and rotation operations. Therefore, if a connection should be changed, the content of the whole read control memory has to be refreshed, whereas for the write control memory only bit related to the modified connection needs to be changed. Therefore an external microprocessor to refresh control memories is used. The refreshing step of control memories is quite crucial, since during the change of the write control memory content, it may happen that in the memory the position of some bytes not involved by the new connection will change. Substantially, this happens because there are some time intervals during which a portion of the memory has to be written under the control of the refreshed control memory, whereas the remaining part is still written under the control of the xe2x80x9coldxe2x80x9d control memory. This is clearly reflected on the read control memory, which has to partially drive the reading operation as a refreshed memory, partially as an xe2x80x9coldxe2x80x9d memory.
A simple solution is to duplicate control memories both in read and write modes. FIG. 3 shows the structure of a knock-out switch memory branch with memory duplication KS2. The input has the data flow DIN, consisting of N frames ST. Reference is made in the following to a frame ST consisting of Virtual Containers VC12, wherein 18 xe2x80x9coverheadxe2x80x9d bytes and 63 data bytes or xe2x80x9cpayloadxe2x80x9d bytes, repeated four times are provided. It should be appreciated that write control memories WCMa and WCMb are provided, one as the reproduction or duplicate of the other, which drive the concentrator rotator block CR through a multiplexer WMUX. A memory DRM, driven by respective read control memories RCMa and RCMb, through a read multiplexer RMUX, is structured as three parallel blocks: an overhead memory block OHMEM, a first memory block DMEM1 and a second memory block DMEM2. The overhead memory block OHMEM is simply used to store the 18 xe2x80x9coverheadxe2x80x9d bytes of the frame ST. The first memory block DMEM1 and the second memory block DMEM2 contain 63xc3x97N/m bytes, respectively. Therefore, memory DRM outputs data flows OHOUT, 1OUT, 2OUT, consisting of N/m frames, which are conveniently selected by an output multiplexer OMUX to form the output data flow OUT. Output frames result delayed by 63 time units TS compared to input frames.
Operations being executed upon arrival of a frame ST at an input IN of the memory DRM are the following:
a) writing the overhead memory OHMEM;
b) starting the writing of first memory block DMEM1;
c) completing the writing of the first memory block DMEM1 and, at the same time, reading the overhead memory OHMEM;
d) writing the second memory block DMEM2 and reading the first memory block DMEM1;
e) writing the first memory block DMEM1 and reading the second memory block DMEM2;
f) writing the second memory block DMEM2 and reading the first memory block DMEM1;
g) writing the overhead memory block OHMEM, subsequently starting writing the first memory block DMEM1 and reading the second memory block DMEM2;
h) completing the writing of the first memory block DMEM1 and reading the overhead memory block OHMEM.
FIG. 3b shows a time diagram of the memory DRM output and input, reporting the above disclosed operation steps.
Said operations are repeated for each subsequent frame ST, so that each portion of the memory DRM is written under control of either updated or old control memories.
When a connection change occurs, control memories need to be refreshed. To maintain synchronism, read control memories RCMa and RCMb have to be refreshed introducing a delay equal to the number of time units TS contained in the frames payload ST, i.e. 63, compared to read control memories WCMa and WCMb. The refreshing step occurs through read control memories RCMb and write control memories WCMb, either duplicate or spare. It is possible, in fact, to refresh the content of duplicate read control memories RCMb and write control memories WCMb, whereas operations on the memory DRM are controlled by read control memories RCMa and write control memories WCMa. Once the refreshing step is over, the write multiplexer WMUX and read multiplexer RMUX will switch and control will be passed to duplicated read control memories RCMb and write control memories WCMb.
This solution can avoid any problems due to unrefreshed control memories based readings. However, it will obviously lead to the use of a large amount of memory, with a consequent increase of space requirements in the circuits and higher circuit costs.
It is the object of the present invention to solve the above drawbacks and provide a switch matrix among the tributaries of a telecommunication network, having a more effective and improved performance.
In this connection, it is the main object of the present invention to provide a switch matrix among the tributaries of a telecommunication network, which requires a smaller number of circuits, resulting in a lower space requirement for the circuits and lower manufacturing costs.
A further object of the present invention is to provide a switch matrix among the tributaries of a telecommunication network, which has read and write control memories of the main memory which can be updated without the need of duplicating said main memory and without incurring read errors of said main memory.
A further object of the present invention is to provide a switch matrix among the tributaries of a telecommunication network, which employs a packing circuit for the bytes to be elaborated, whose structure is more compact and efficient compared to other known solutions.
A further object of the present invention is to provide a switch matrix among the tributaries of a telecommunication network, which distributes incoming data flows in order to reduce the complexity of the memory managing logic circuits.
In order to achieve such objects, the present invention provides a switch matrix among the tributaries of a telecommunication network incorporating the features of the annexed claims, which form an integral part of the present description.
According to one aspect of the present invention there is provided a switch matrix among the tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data arranged according to SDH protocol, said switch matrix comprising a set of parallel branches, each of said branches comprising at least a first space stage which is able to select and pack, from the input data flow, a subset of data to be exchanged, a second time stage which is able to store the data subset to be exchanged and comprising a random access memory device associated with a write memory and a read memory, said write memory and read memory being driven by a microprocessor and a master counter, wherein the read memory and write memory related to each random access memory device are updated together with a spare read memory which is common to read memories on all branches in parallel and with a spare write memory which is common to write memories on all branches in parallel, respectively.